1. Field of the Invention
The present invention relates to a threshold voltage adjustment method of a non-volatile semiconductor memory device, which allows memory data to be electrically rewritten and a non-volatile semiconductor memory device. Particularly, the present invention relates to adjustment of the threshold voltage of the memory cell after data is erased.
2. Description of Related Art
As shown in FIG. 11, in an N-type memory cell of a non-volatile semiconductor memory device represented by a flash memory, a floating gate FG is formed through an insulation film over a channel region between a source region S and a drain region D and further, a control gate CG is formed through an insulation film on the floating gate FG. Data is memorized by a difference in threshold voltage of the memory cell, which depends on whether or not an electrons e are accumulated on the floating gate FG. A state in which the threshold voltage is kept low because the electrons e are discharged from the floating gate FG is regarded as a memory state of data “1” and a state in which the threshold voltage is kept high because the electrons e are accumulated is regarded as a memory state of data “0”.
Write of data into the memory cell is carried out by injecting electrons e into the floating gate FG of the memory cell, which is a write-in object, with a state in which electrons e are discharged from the floating gates FG of all the memory cells (memory state of data “1”) as an initial state. The write-in operation refers to writing “0” data into the memory cell and this operation is called program operation.
To make all the memory cells into the initial state, prior to the program operation, erase operation, which is discharging electrons e from the floating gate so as to produce the memory state of data “1”, is necessary. This erase operation is carried out by discharging electrons e using FN tunneling phenomenon. This is done under a condition in which with the control gate CG as a negative voltage (=−V), a back gate which constitutes the channel region is brought into a positive voltage (=+V) (case for channel erase). Although not shown here, there is also a method of making the source region S into a positive voltage (=+V) (case of source erase). In case of a flash memory in which the erase operation is executed in each unit of a sector or the like in batch, the state of all the memory cells in the sector needs to be in the “0” data memory state prior to discharging electrons e or the floating gate FG needs to keep electrons e. Consequently, electrons e can be discharged in batch from the floating gates FG of all the memory cells. FIG. 12(A) shows a distribution of the threshold voltage of the memory cell in data erase operation. If the erase operation is executed, distribution of high threshold voltage, which is “1” data memory state, is changed to distribution of low threshold voltage.
After the erase operation, the memory data turns into “1”, data memory state. In this case, the maximum value of the threshold voltage is desired to be set low from viewpoints of margin of data readout. After the erase operation is executed in batch, distribution of the threshold voltage comes to have a predetermined expansion because of characteristic variation due to manufacturing reason and characteristic variation of individual memory cells originating from asymmetry in chip layout, application voltage or the like. Thus, as shown in a region (I) of FIG. 12(A), there may exist a memory cell indicating depletion characteristic in which the threshold voltage lowers below 0V. This is so-called over-erase state. Such a memory cell in the over-erase state is subjected to threshold voltage adjustment of raising the threshold voltage by injecting hot electrons e into the floating gate FG by applying a voltage bias similar to the program operation (FIG. 12(B)). This is so-called auto program disturb after erase (APDE) operation. As for voltage stress upon the APDE operation, with a positive voltage applied to a drain region D with respect to a source region S, a gate voltage, which will be described later, is applied to a control gate CG. An over-erase memory cell having a threshold voltage lower than the gate voltage is conductive so as to inject electrons e into the floating gate FG so that the threshold voltage is raised.
FIG. 13 shows a basic circuit block diagram upon the APDE operation. Each drain terminal of a memory cell group 100 is connected to a common bit line BL and the bit line BL is connected to a drain voltage generating circuit 400. Upon the APDE operation, the drain voltage generating circuit 400 applies a positive voltage VPP to the bit line BL and supplies it to the drain terminal of the memory cell group 100. Each gate terminal is connected in common and maintained to have a voltage difference of 0V with respect to the source terminal (VG=VS=0V). The drain voltage VD becomes a positive voltage VPP (VD=VPP) in a range of voltage supply capacity of the drain voltage generating circuit 400. Therefore, if there exist many memory cells having depletion characteristic (region (I) of FIG. 12(A)), a large amount of current is required for adjustment of the threshold voltage and the positive voltage applied to the drain terminal may lower depending on the capacity of the drain voltage generating circuit 400 so that the adjustment efficiency also drops, thereby taking much time for the APDE operation. Here, it can be considered to use a boosted voltage with respect to the power source voltage VCC as the positive voltage VPP. In this case, a charge pump circuit or the like can be considered as the drain voltage generating circuit 400.
As a conventional technology considering shortage of the APDE operation time, Japanese Laid-Open Patent Publication No.8-55487 has disclosed a method in which correction of the threshold voltage of an over-erase memory cell is started with a gate voltage VG of a negative voltage (for example, VG=−1.0V) instead of the gate voltage VG in FIG. 13 and the gate voltage VG is increased by step until the memory cell reaches a desired minimum threshold voltage. For example, as shown in FIG. 14, with the source voltage VS of 0V and drain voltage VD of 6.0 V, the gate voltage VG of −1.0V, −0.75V, −0.5V, −0.25V is applied by step. Consequently even an over-erase memory cell is not conductive if its threshold voltage is higher than the gate voltage VG of a negative voltage so that current necessary for adjustment operation is reduced. As a result, the circuit size of the drain voltage generating circuit 400 which outputs the positive voltage VPP can be reduced.
However, under a bias condition in which the gate voltage VG is 0V of FIG. 13, all the over-erase memory cells having the depletion characteristic that the threshold voltage is a negative voltage come to be conductive. For the reason, under a condition having a large distribution (region (I) in FIG. 12(A)) of over-erase memory cells each whose threshold voltage turns to a negative voltage upon the erase operation, all the memory cells belonging to the region (I) come to be conductive in the APDE operation so that a large drain current flows. If this drain current increases over the supply capacity of the drain voltage generating circuit 400, the drain voltage VD lowers from the positive voltage VPP. As a result, voltage stress to the drain terminal lowers so that the quantity of hot electrons is reduced thereby worsening injecting efficiency of electrons into the floating gate FG. Consequently, the APDE operation time is prolonged and depending on case, adjustment itself of the threshold voltage may be disabled.
According to a method of increasing the gate voltage VG by step by starting from a negative voltage as indicated in FIG. 14, an applied voltage and applied time for each step are predetermined. On the other hand, the operation characteristic of the memory cell has a predetermined expansion because of characteristic variation due to difference in usage condition such as environmental temperature and operation voltage as well as characteristic variation of each memory cell originating from manufacturing. Thus, when the gate voltage VG is set up for the APDE operation, a sufficient allowance needs to be secured so that the sum of the drain current does not reach a limit of the current supply capacity of the drain voltage generating circuit 400. In each step, the number of the over-erase memory cells to be conductive is limited and the gate voltage VG is set up so that the sum of the drain current is settled within the current supply capacity of the drain voltage generating circuit 400. For the reason, the APDE operation cannot be carried out at the maximum capacity of the drain voltage generating circuit 400 so that it may take a large amount of time for the APDE operation.